An interconnect circuit board is the physical realization of electronic circuits or subsystems from a number of extremely small circuit elements electrically and mechanically interconnected on a substrate. It is frequently desirable to combine these diverse type electronic components in an arrangement so that they can be physically isolated and mounted adjacent one another in a single compact package and electrically connected to each other and/or to common connections extending from the package.
Complex electronic circuits generally require that the circuit be constructed of several layers of conductors separated by insulating dielectric layers. The conductive layers are interconnected between levels by electrically conductive pathways through the dielectric called vias. Such a multilayer structure allows a circuit to be more compact.
One well known method for constructing a multilayer circuit is by sequentially printing and firing thick film conductors and insulating dielectrics on a rigid insulative substrate such as alumnia. The alumina substrate provides mechanical support and also X-Y dimensional stability and facilitates registration to the patterned thick film conductors and dielectric layers. However, the thick film process has a disadvantage in that printing through a screen mesh can result in pinholes or voids in the dielectric layer which can cause shorting between conductor layers. If a thick film dielectric is formulated to allow sufficient flow of the paste during the printing operation and thus to minimize the tendency to form pinholes, then the maintenance of small vias is likely to be compromised by the flow of dielectric paste into the via hole. Also, the repetitive printing and firing steps for each layer are time consuming and expensive.
Another prior art method for constructing multilayer circuits is that of co-firing a multiplicity of ceramic tape dielectrics on which conductors have been printed with metallized vias extending through the dielectric layers to interconnect the various conductor layers. (See Steinberg, U.S. Pat. No. 4,654,095.) These tape layers are stacked in registry and pressed together at a preselected temperature and pressure to form a monolithic structure which is fired at an elevated temperature to drive off the organic binder, sinter the conductive metal and densify the dielectric. This process has the advantage that firing need only be performed once, thus saving fabricating time and labor and limiting the diffusion of mobile metals which could cause shorting between conductors. However, this process has the disadvantage that the amount of shrinkage which occurs on firing may be difficult to control. This dimensional uncertainty is particularly undesirable in large complex circuits and can result in misregistration during subsequent assembly operations.
On the other hand, Vitriol and Brown in U.S. Pat. No. 4,645,552 disclose a process for constructing a multilayer circuit on a rigid substrate which is similar to the thick film process described above in the way that circuit layers of conductors and dielectrics are sequentially added to the circuit and fired. The circuit is fabricated on a rigid, dimensionally stable substrate by a sequence of steps such as the following:
(a) forming a conductor pattern on a dimensionally stable substrate; PA0 (b) forming via holes in a dielectric green tape; PA0 (c) laminating the green tape onto the substrate in registry with the conductor patterns; PA0 (d) firing the substrate, conductor and green tape; PA0 (e) metallizing the top surface of the dielectric tape and filling the vias; and PA0 (f) repeating steps (b) and (e) until the multilayer structure is complete. PA0 (a) providing a dimensionally stable electrically insulative substrate; PA0 (b) applying to the substrate a patterned conductive layer; PA0 (c) firing the patterned conductive layer; PA0 (d) laminating to the fired patterned conductive layer and exposed areas of the substrate a layer of dielectric green tape; PA0 (e) forming vias in selected positions through the layer of dielectric green tape in registration with the fired patterned conductive layer of step (c); PA0 (f) firing the laminated dielectric green tape layer; PA0 (g) filling the vias in the dielectric tape layer with a conductive metallization; PA0 (h) firing the filled vias in the dielectric tape layer; PA0 (i) applying a patterned conductive layer to the dielectric tape layer in registry with the vias therein; PA0 (j) firing the patterned conductive layer; and PA0 (k) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (d) through (j) until the desired number of circuit layers has been obtained. PA0 (a) providing a dimensionally stable substrate; PA0 (b) laminating to a surface of the substrate a layer of dielectric green tape; PA0 (c) optionally forming vias in the laminated green tape; PA0 (d) firing the laminated dielectric green tape layer; PA0 (e) filling any vias in the laminated dielectric tape with a conductive metallization; PA0 (f) firing any filled vias in the dielectric tape layer; PA0 (g) applying to the dielectric tape layer a patterned conductive layer; PA0 (h) firing the patterned conductive layer; PA0 (i) laminating a dielectric green tape layer to the fired patterned conductive layer and exposed areas of the underlying dielectric tape layer; PA0 (j) forming vias in the laminated green tape layer of step (i); PA0 (k) firing the laminated green tape layer which was applied in step (j); PA0 (l) filling the vias in the tape layer with a conductive metallization; PA0 (m) firing the filled vias contained in the dielectric tape layer from step (l); PA0 (n) applying to the dielectric tape layer from a patterned conductive layer; PA0 (o) firing the patterned conductive layer from step (n); and PA0 (p) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (i) through (o) until the desired number of circuit layers has been obtained.
Such a process eliminates some of the disadvantages of the thick film multilayer circuit fabrication process because the risks of pinholes and via closure are eliminated due to the fact that green tape is used as a dielectric insulating layer and mechanically punched vias are employed. However, there is a risk that the flexible tape will be distorted in handling after via formation, which may cause misregistration with the conductor pattern on the substrate.
Rellick, in U.S. Pat. No. 4,655,864, discloses a dielectric green tape suitable for lamination onto a rigid substrate. This green tape is used in a process which is similar to the thick film process described above in the way that circuit layers of conductors and dielectric are sequentially added to the circuit and fired. By using a dielectric in tape form, the risk of pinholes and via closure inherent in the thick film process are eliminated. The tape is comprised of glass and refractory oxides dispersed in an organic binder and is especially suitable for laminating onto rigid substrates. The method for forming a multilayer interconnect structure disclosed in this patent, however, also contemplates forming vias in the dielectric tape before lamination with the attendant disadvantages discussed above.